The present invention relates to the field of electronic circuits, and, more particularly, to a chronometer.
A chronometry type electronic circuit is illustrated in FIG. 1. This circuit is designed for the digital measurement of the time intervals between short electronic signals Sgn delivered by a sensor, or other circuits of an electronic system. The circuit of FIG. 1 has a generator CLK of periodic pulses H used as a clock signal for a counter CNT, which counts the periodic pulses during each time interval between two signal Sgn pulses. The counter CNT receives a resetting signal at a resetting input Rst for each pulse between two time intervals. The result of the counting is stored in a register REG of the circuit. The result Mes, which represents the digital measurement of a time interval expressed in a number of clock periods, is available at the output of the register REG so that it can be used by the other circuits of the system.
In order that the transfers of the counting results may be done appropriately, the activation Enb of the register REG immediately precedes the resetting Rst and the reactivation Enb of the counter CNT. A logic gate DEL causes a delay by a period t in the transmission of the pulses of the resetting Rst signal between the register Reg and the counter CNT, i.e., from an instant T to an instant T+t.
One drawback of these conventional measurement circuits is that they limit the range of measurement to the capacity of the counter and of the register. The capacity refers to a binary format or number of bits. Another drawback is that the relative error of the digital measurements becomes considerable during the measurement of short time intervals. Ultimately, the measurement of a time interval approximately equal to the period H of the clock signal CLK is effected by an error of one bit on the measurement of one bit, giving a relative error of 100%.
The only way to increase the measuring precision of a circuit of this kind is to increase the clock frequency. However, this adversely effects the range of measurement unless the capacity of the counter and of the register used to make the circuit is increased. The binary format is dictated by the electronic system into which the measuring circuit is integrated. Thus, systems for the control of asynchronous motors, such as those for electronic home appliances, are generally formed by an 8-bit or 16-bit microcontroller for manufacturing cost reasons.
An object of the invention is to provide an electronic circuit for the measurement of time intervals that overcomes the above described drawbacks.
Thus, the object of the invention is to make a circuit for the measurement of time intervals that combines a wide range of measurements with high precision while limiting the capacity, or more specifically, the binary format of the digital measurements.
This object is achieved by providing for the self-calibration of the measurement circuit as a function of the order of magnitude of the previous measurements of time intervals. A programmable frequency divider is inserted between the pulse generator and the counter to mark the frequency of the periodic pulses that set the pace of the counter. The programming of the frequency division is corrected as a function of the changes in the magnitude of the measurement results.
A time interval measurement circuit according to the present invention comprises a generator of primary periodic pulses, a frequency divider capable of transmitting secondary periodic pulses for scaling down the frequency of the primary periodic pulses, and means for counting the secondary periodic pulses transmitted during the measured time interval. The frequency divider is programmable by a digital factor that determines the frequency division. The circuit comprises self-calibration means capable of modifying the digital factor as a function of the number of pulses counted by the counting means during a previous time interval measurement. Preferably, the divider scales down the frequency of the transmitted periodic pulses by the digital factor raised to the power of two.
The self-calibration means preferably comprises a negative feedback loop incrementing the digital factor when the number of pulses counted by the counting means is greater than a threshold. Preferably, the negative feedback loop increases the digital factor by an increment when the number of pulses is greater than a maximum threshold, and reduces the digital factor by a decrement when the number of pulses is below a minimum threshold. Otherwise, the negative feedback loop does not modify the digital factor when the number of pulses is between the minimum threshold and the maximum threshold.